It is necessary to handle burst data in, e.g., PON (Passive Optical Network) systems that have been developed as a technique of implementing FTTH (Fiber To The Home). In these systems, a CDR circuit is indispensable which instantaneously establishes phase lock with asynchronously received burst data, extracts a clock in phase with the burst data, and outputs the data retimed in synchronous with the clock. A circuit of this type is disclosed in, e.g., reference, Yusuke Ota et al., “High-Speed, Burst-Mode, Packet-Capable Optical Receiver and Instantaneous Clock Recovery for Optical Bus Operation”, IEEE Journal of Lightwave Technology, Vol. 12, No. 2, pp. 325-331, February 1994.
FIG. 17 shows an example of the arrangement of a CDR circuit 200 used for this application purpose. Reference numeral 201 denotes a flip-flop; 202, a main VCO (Voltage Controlled Oscillator); 203, a sub VCO, and 204, a phase comparator. The phase comparator 204 compares a reference clock 222 having the same frequency as a data rate frequency f1 of input data 220 with the phase of the oscillation output of the sub VCO 203, and outputs a frequency control signal 224 which makes the phases match. The frequency control signal 224 is input to the main VCO 202 and the sub VCO 203. Hence, the frequency of a recovered clock 223 output from the main VCO 202 is the same as that of the reference clock 222. The main VCO 202 receives the input data 220 and performs adjustment to make the phase of the recovered clock 223 match with that of the data 220 using the voltage transition point of the input data 220 as a trigger. The recovered clock 223 in phase with the input data 220 is used to retime the input data 220 in the flip-flop 201. The data 220 input to the flip-flop 201 is adjusted using a stationary delay circuit (not shown) to reliably extract a clock.